What is an ETAP Short Circuit Analysis?

An ETAP Short Circuit Analysis is a comprehensive power system study that calculates prospective fault currents during multi-phase and ground fault conditions. Using industry-standard ETAP software, the study verifies if switchgear, cables, and busbars can withstand maximum prospective fault currents, establishing critical baseline data for relay coordination and arc flash studies.

What is the difference between IEC 60909 and IEEE 551 methodologies in fault calculations?

IEC 60909 is a standard used globally and across India that calculates maximum and minimum short-circuit currents using an equivalent voltage source at the fault location. IEEE 551 (the Violet Book) is the North American standard utilizing multi-multiplying factors for calculating asymmetrical fault currents at specific intervals after fault inception. Sparrow RMS provides dual-methodology reporting to match any equipment specification.

Why is utility grid impedance data critical for short circuit studies in India?

Utility grid impedance defines the fault contribution from the electrical utility grid supply point. In India, obtaining verified Thevenin equivalent impedance data from regional DISCOMs or STUs can be complex. Relying on default assumptions often yields under-designed layouts (creating massive safety hazards) or overly conservative over-designed systems that balloon equipment procurement budgets.

How often should an industrial facility update its short circuit analysis?

A short circuit analysis should be updated every 3 to 5 years, or immediately when significant changes occur in the network. Key triggers include adding new generation sources (such as captive power or solar arrays), replacing transformers, altering major motor loads, or when the local DISCOM upgrades its local substation network infrastructure.

What are the primary risks of running an electrical network with under-rated switchgear?

Operating an industrial network with under-rated switchgear risks catastrophic equipment destruction, severe arc flash incidents, injuries to personnel, and extended plant down-time. If a breaker cannot handle the physical making or breaking duty during a fault, it can violently fail or explode instead of isolating the network anomaly safely.

Short Circuit
Analysis Services (ETAP)

Overview

Short Circuit Analysis calculates the fault currents that flow in a power system during three-phase, single line-to-ground, line-to-line, and double line-to-ground fault conditions. The results are used to verify that all switchgear, busbars, cables, and protective devices are rated to withstand the maximum prospective fault current at their location — and to provide the fault level data required for relay coordination and arc flash studies. It is a mandatory study for any new electrical installation and for any existing system that has undergone significant modification.

What the Study Covers

Comprehensive Network Fault Analysis

Using ETAP's Short Circuit module in accordance with both IEC 60909 and ANSI/IEEE methodologies, the study provides complete fault level data across the entire network:

1. Three-Phase Symmetrical Calculations

Three-phase symmetrical fault current (\(I''_{k3}\)) at all busbars — the basis for equipment breaking capacity verification

2. Single Line-to-Ground Analysis

Single line-to-ground fault current (\(I''_{k1}\)) — typically the highest fault current in solidly earthed systems

3. Asymmetrical Fault Assessment

Line-to-line and double line-to-ground fault currents for complete asymmetrical fault assessment

4. Peak Current & DC Offset

Peak fault current (\(i_p\)) and DC offset — required for switchgear making capacity verification

5. Breaking Duty Configurations

Breaking duty current at the instant of contact separation — for circuit breaker selection and verification

6. Multi-Source Contributions

Contribution from all sources: utility grid, generators, synchronous motors, and induction motors

7. Equipment Adequacy Benchmarking

Equipment adequacy check: comparison of calculated fault currents against rated breaking, making, and withstand capacities of all switchgear and busbars

8. Fault Level Margin Mapping

Fault level margin assessment: identification of locations where fault current is approaching equipment limits

Applicable Compliance Standards

IEC 60909-0

Short-circuit currents in three-phase AC systems — calculation methods
ANSI/IEEE C37 Series

IEEE switchgear standards including fault current ratings and testing requirements
IEEE 551 (Violet Book)

IEEE Recommended Practice for Calculating AC Short-Circuit Currents in Industrial and Commercial Power Systems
IS 13234

Indian Standard guide for calculation of short-circuit currents

Typical Engineering Applications

Short circuit analysis is required for all new electrical installations, any system modification that increases fault level (new generation, network interconnection, transformer replacement), and as part of periodic safety and compliance reviews for industrial and utility networks.

New Installations Network Expansion Utility Upgrades Asset Replacement

Strategic Benefits

Confirms that installed switchgear is rated for the actual fault current at its location — preventing catastrophic breaker failure during a fault

Failure Mitigation

Identifies locations where equipment is under-rated, enabling targeted replacement before a failure occurs

Setting Foundations

Provides the fault current data required for relay setting calculations and arc flash incident energy analysis

Compliance Assurance

Satisfies insurance, regulatory, and lender requirements for documented equipment adequacy verification

Procurement Design

Supports procurement specifications for new switchgear with correctly calculated required ratings

Why We Are the Best for Short Circuit Analysis in India

Short-circuit analysis appears straightforward in principle, but its accuracy depends critically on correct source impedance data — particularly the utility grid equivalent impedance at the point of supply. In India, obtaining verified Thevenin equivalent impedance data from DISCOMs and STUs is not always straightforward, and using default or overly conservative assumptions can lead to both under-designed systems (where fault levels are understated) and over-designed systems (where excessive margins inflate costs). Our team has developed established relationships and documented procedures for obtaining and verifying utility impedance data for projects across multiple Indian states.

We perform short circuit analysis in accordance with both IEC 60909 and IEEE methodologies, which is important because Indian projects frequently involve equipment specified to either standard. Our ETAP models are shared directly with the relay coordination and arc flash teams, eliminating the risk of inconsistent fault level assumptions across different studies — a common and serious problem when these studies are performed by different firms.

Dual-Methodology Capability

IEC 60909 and IEEE 551 dual-methodology capability — matching the standard used for equipment specification

Utility Coordination Expertise

Established process for obtaining and verifying DISCOM/STU grid impedance data for Indian projects

Unified Model Sharing

Integrated model sharing with relay coordination and arc flash studies: one consistent fault level dataset

Targeted Engineering Reporting

Equipment adequacy reporting formatted for direct use in procurement, insurance, and regulatory submissions

Fault Growth Forecasting

Fault level growth forecasting: assessment of future fault level increases as the network evolves, enabling forward-looking equipment rating decisions

Ensuring your switchgear is rated for what it will actually experience.